Straightedge blog Mechanisms simulated, asserted, and animated from the simulation. https://scimigo.github.io/straightedge/posts/ 2026-08-18T00:00:00Z SciMigo Matrix multiplication, four ways https://scimigo.github.io/straightedge/posts/matrix-product-four-ways.html 2026-08-18T00:00:00Z AB is taught as a rule for filling in entries. Three other readings of the same product — by column, by row, and as a sum of rank-1 terms — explain what a matrix product is for, and two of them are what a systolic array and tensor parallelism already execute. Why the systolic array feeds itself diagonally https://scimigo.github.io/straightedge/posts/systolic-skew.html 2026-08-17T00:00:00Z The diagonal in a systolic array is not a drawing convention. Entries entering on cycle t are exactly the anti-diagonal m + k = t, because that is the only arrival time at which a multiply meets the running sum it belongs to. Ring all-reduce: the bytes per rank don't grow https://scimigo.github.io/straightedge/posts/ring-allreduce.html 2026-08-17T00:00:00Z A ring all-reduce moves 2(N-1)/N times the buffer per rank — under 2D at every ring size, 1.5D at four ranks and 1.97D at sixty-four. Adding ranks does not cost bytes. What grows is the number of serial round trips. The pipeline bubble 1F1B doesn't fix https://scimigo.github.io/straightedge/posts/pipeline-bubble.html 2026-08-17T00:00:00Z GPipe and 1F1B finish on the same cycle and idle for the same number of stage-slots. What 1F1B changes is activation memory — 23 sets against 6 — and that is the trade that decides whether a model fits.